1. Field of the Invention
The present invention relates to interdigitated leads-over-chip lead frames and other devices and methods for supporting integrated circuit dice.
2. State of the Art
Integrated circuit (IC) dice or "chips" are small, generally rectangular IC devices cut from a semiconductor wafer, such as a silicon wafer, on which multiple IC's have been fabricated. Bare IC dice are typically packaged to protect them from corrosion by attaching them to a lead frame for support and heat conduction and then enclosing them in a die package.
Examples of conventional type lead frames having interdigitized lead frame strips and/or lead fingers thereon are illustrated in U.S. Pat. Nos. 4,949,161 and 5,147,815.
A conventional die package 10 including a type of lead frame referred to as a "Leads-Over-Chip" (LOC) lead frame 12 is shown in a cut-away view in FIG. 1. The LOC lead frame 12 includes an assembly of conductive leads 14, each having an underside attachment surface adhesively attached to a front-side surface of an IC die 16 using double-sided adhesive tape 18 so the assembly of conductive leads 14 physically supports the IC die 16 within the die package 10. Each conductive lead 14 is wire-bonded to one of a multitude of bond pads on the front-side surface of the IC die 16, and each conductive lead 14 extends from the die package 10 to terminate in a pin that may be connected to external circuitry (not shown) so circuitry within the IC die 16 may communicate with the external circuitry through the bond pads and the conductive leads 14. Of course, while the conductive leads 14 are shown in FIG. 1 as being wire-bonded to bond pads extending along a center axis of the front-side surface of the IC die 16, it will be understood that the leads of a LOC lead frame may also be wire-bonded to bond pads extending about the perimeter of the front-side surface of an IC die.
In another conventional 16 Meg. DRAM semiconductor memory device package for NEC Corporation, a die package 210 including a type of lead frame referred to as a "Leads-Over-Chip" (LOC) lead frame 212 is shown in a top view in FIG. 1A. The LOC lead frame 212, includes an assembly of conductive leads 214 each having an underside attachment surface adhesively attached to a front-side surface of an IC die 216 using double-sided adhesive tape (not shown) so the assembly of leads 214 physically supports the IC die 216 within the die package 210. Each conductive lead 214 is wire-bonded to one of a multitude of bond pads on the front-side surface of the IC die 216, and each lead 214 extends from the die package 210 to terminate in a pin that may be connected to external circuitry (not shown) so circuitry within the IC die 216 may communicate with the external circuitry through the bond pads and the conductive leads 214. As shown, the leads 214 in FIG. 1A are wire-bonded to bond pads extending along a single side axis of the front-side surface of the IC die 216.
In yet another conventional 4 Meg..times.4 DRAM semiconductor memory device package for NEC Corporation, a die package 310 including a type of lead frame referred to as a "Leads-Over-Chip" (LOC) lead frame 312 is shown in a top view in FIG. 1B. The LOC lead frame 312 includes an assembly of conductive leads 314, each having an underside attachment surface adhesively attached to a front-side surface of an IC die 316 using double-sided adhesive tape (not shown) so the assembly of leads 314 physically supports the IC die 316 within the die package 310. Each conductive lead 314 is wire-bonded to one of a multitude of bond pads on the front-side surface of the IC die 316, and each lead 314 extends from the die package 310 to terminate in a pin that may be connected to external circuitry (not shown) so circuitry within the IC die 316 may communicate with the external circuitry through the bond pads and the conductive leads 314. As shown, the leads 314 in FIG. 1B are wire-bonded to bond pads extending along a single side axis of the front-side surface of the IC die 316.
LOC lead frames are well-known in the art, and are described in various embodiments in U.S. Pat. Nos. 4,862,245, 5,218,168, 5,250,840, 5,256,598, 5,381,036, 5,521,426, and 5,563,443.
Conventional LOC lead frames can sometimes be problematic because the arrangement and design of their leads do not allow the leads to cover an optimum percentage of the surface area of an IC die when attached to the die. As a result, the leads are unable to support the die as well as desired, and the leads do not extract as much heat as desired from the die.
In yet another type of lead frame configuration, a lead-under-chip type lead frame, illustrated in U.S. Pat. No. 5,360,992, the lead fingers extend under and beyond the semiconductor device, acting as a die paddle for the device, with `````wire bonds being formed between the bond pads located on the active surface of the semiconductor device and portions of the lead fingers extending therebeyond. This type of lead frame arrangement requires the use of long lead fingers to extend the length of the semiconductor device and therebeyond for wire bonding purposes, thereby affecting the response time of the semiconductor device assembly.
In still yet another type of lead frame and integrated circuit package, as illustrated in U.S. Pat. No. 5,585,668, two integrated circuit semiconductor devices are connected to a common, substantially planar lead frame, wherein the bond pads on each active surface of a semiconductor device face the common lead frame and are wire bonded to the lead fingers thereof.
Also, it can be difficult to produce die packages having "mirror image" pin-out arrangements using conventional LOC lead frames. A pair of such mirror image die packages has one set of die functions (e.g., V.sub.CC, DQ1, DQ2, WE*, RAS*, A10, A0, A1, A2, and A3) associated with the left-side pins of a first one of the pair and the right-side pins of a second one of the pair, and has another set of functions (e.g., V.sub.SS, DQ4, DQ3, CAS*, OE*, A9, A8, A7, A6, A5, and A4) associated with the right-side pins of the first one of the pair and the left-side pins of the second one of the pair. Such mirror image die packages can be useful, for example, when a pair of die packages are positioned opposite one another on opposing sides of a Single In-line Memory Module (SIMM) board and share the same conductors for identical functions. The difficulty in producing a pair of mirror image die packages using conventional LOC lead frames arises because producing the pair traditionally requires: a pair of mirror image dice and identical LOC lead frames, as described in U.S. Pat. Nos. 5,508,565 and 5,530,292; identical dice and a pair of mirror image LOC lead frames, as described in U.S. Pat. No. 5,508,565; or wire-bonding a central row of bond pads on one of the pair of dice to one of an identical pair of LOC lead frames and then reverse-wire-bonding a central row of bond pads on the other of the pair of dice to the other of the pair of LOC lead frames.
Because the traditional methods of producing mirror image die packages using mirror image dice and mirror image LOC lead frames require the production of an additional part, they are inefficient and expensive methods. In addition, using only dice with a central row of bond pads to make mirror image die packages is undesirably restrictive, since many dice have a different arrangement of bond pads.
Therefore, there is a need in the art for an LOC lead frame and other devices and methods for supporting IC dice in an improved manner. Such a LOC lead frame should be capable of producing mirror image die packages, if desired, using identical dice having a wide variety of different bond pad arrangements. The lead frame should also conduct heat away from a die in an improved manner.